#543 PLL Ramp Generator

A simple CD4046 ramp generator circuit from a design by M.S. Nagaraj published in Elektor 7/1994.

Notes

The VCO in the DC4046 normally produces a triangular signal, but this circuit arrangement generates a saw. The original circuit was by M.S. Nagaraj and published in Elektor Magazine 7/1994.

The saw tooth is achieved by significantly off-setting the rise and fall times of the VCO by using C1a capacitor value much greater than the C1b capacitor. The capacitor(s) on C1a and C1b set the VCO frequency.

So - not a perfect saw tooth, but very close.

In the circuit I test here, C1a = 1nF, and C1b = 10pF, so a resulting frequency difference of 100:1.

Constructionlished

Performance

With VR1 adjusted for minimum freuqency of ~3.5kHz:

With VR1 adjusted for maximum freuqency of ~128.9kHz:

Credits and References

• CD4046 Datasheet
• PLL-controlled ramp generator - published in Elektor Magazine 7/1994, page 102