#319 555Timer/DigitalLogicClock

Build a flexible, low-frequency digital logic clock module.

Build

Notes

This digital clock module was designed by Ben Eater as part of his 8-bit computer build. It is also an interesting demonstration of the 555 timer in all its major modes of operation.

The clock module features in summary:

5V CMOS & TTL compatible output
relatively low frequency operation
variable frequency automatic (continuous) mode
manual mode - trigger individual clock pulses by hand
switch between auto and manual mode with button debounce
HALT override to disable all clock output
LED indicator of the clock output

Automatic (Astable) Mode

The first 555 timer (IC1) is configured in astable mode with variable frequency. It can generate pulses from:

0.71Hz @ 50% duty, to
58Hz @ 60% duty

This is the source of the automatic (continuous) clock.

Manual (Monostable) Mode

The second 555 timer (IC2) is configured in monostable mode. When switch S1 is pressed, it generates a single pulse:

110ms high time

This is the source of the manual trigger clock.

Selector (Bistable)

The third 555 timer (IC3) is configured as a bistable debouncer for switch S2. Switch S2 selects between the automatic and manual clock source.

The selection is implemented with NAND gate logic on IC4

Halt

Switch S3 is combined with NAND gate logic on IC5 to provide a master enable/disable switch.

Combining the Signals

There are four inputs that need to be resolved into the final output:

(a) Automatic (Astable) input
(b) Manual (Monostable) input
(c) Selector input
(d) Halt input

The basic logic can be intuited: d'.(a.c + b.c')

I verified that with a Karnaugh map analysis. I decided to go with the idea of converting this to an implementation solely based on NAND gates.

DigitalLogicClock_logic

Construction

Breadboard

Schematic

Breadboard build and test:

DigitalLogicClock_bb_build

Layout for a protoboard implementation:

DigitalLogicClock_protoboard_layout

Protoboard build: