#689 Programmable Frequency Reference

Build and test a programmable frequency reference capable of dialing in 4095 discrete frequencies between 488Hz and 1MHz.

Notes

I discovered this interesting little circuit in ARRL’s Hands-on Radio Experiments Volume 2 by H. Ward Silver. It is Experiment 97, p91.

How if Works

The essentials:

• the CD4001is used as a Pierce oscillator to generate a 4MHz crystal-locked clock signal and it’s complement
• the clock drives the 4040 ripple counter
• a series of DIP switches enable the corresponding ripple counter output positions to pull the J-input low on the 74LS73 J-K Flip-Flop
• when the J-input on the 74LS73 J-K Flip-Flop is:
  • low: it causes the output Q to go low on the falling edge of the clock input
  • high: it causes the output Q to toggle on the falling edge of the clock input
  • NB: the clock input is the complement of the main clock (out of phase)
  • when output Q goes high, it triggers the reset of the 4040 ripple counter and also clocks the second 74LS73 J-K Flip-Flop
• the second 74LS73 J-K Flip-Flop is used to convert the output of the first flip-flop to a symmetric waveform

The resulting frequencies for clock frequency f given the DIP switches set to the binary value B:

• first 74LS73 Flip-Flop output:
  • frequency: f/(B + 1)
  • but is not symmetrical (will be a high pulse with duration of 1/f for all frequencies i.e <= 50% duty)
• second 74LS73 Flip-Flop output:
  • half the frequency of the first 74LS73 Flip-Flop output i.e.
  • frequency: f/((B + 1) * 2)
  • but it is a symmetrical (50% duty) square wave

The following timing diagram illustrates the logic for two cases:

• left: DIP selected Q1 (i.e. 001b)
• left: DIP selected Q2 (i.e. 010b)

Note: The original CD4027 flip-flop logic is slightly different because it transitions on the rising edge, but the end result is the same

Circuit Design

I have made some part substitutions and minor changes to the circuit as follows:

• CD4001 instead of 74HC4001
• 74LS73 instead of CD4027
• CD4040 instead of 74HC4040
• added one inverter from the CD4001 to buffer the oscillator output

Breadboard Test Results

Output frequency by DIP switch selection. Some values from the 4095 possibilities (0 is not a valid configuration).

Some sample scope traces where:

• CH1 Yellow: 74LS73 Q2 (final output)
• CH2 Blue: clock
• CH3 Red: 74LS73 Q1 (final output)

DIP 000000000001b, expected output frequency 1MHz:

DIP 000000000111b, expected output frequency 250kHz:

Protoboard Build

Credits and References

• ARRL’s Hands-on Radio Experiments Volume 2 - H. Ward Silver, Experiment 97, p91
• CD4001 datasheet
• CD4027 datasheet Dual J-K Master/Slave Flip-Flop with Set and Reset
• CD4040 datasheet
• 74LS73 Datasheet Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs