#207 FrequencyCounter

Test a CMOS frequency counter circuit with a 100Hz - 5MHz range

Notes

I found this circuit published in Electronics magazine (Sep 16 1976).

It’s a classic demonstration of the CD4026 “bucket-brigade” and CD4047 astable oscillator.

Sample/Display Time configuration

The frequency counter is governed by a CD4047 oscillator. Since this offers a clean 50% duty cycle, it is ideal for flipping the circuit between two modes:

sampling period
display period

The frequency is tuned with 10nF and a resistor network comprising 2 x 220kΩ and a 20kΩ pot. Thus the frequency limits are expected to be between about 49Hz and 51Hz.

At 50Hz, the cycle time is 20ms. At 50% duty cycle, that’s 10ms for sampling and 10ms for display.

So given the frequency count displayed is based on a 10ms sample, the reading is therefore in tenths of a kHz. The decimal point is enabled on the second digit in the display so the result may be easily read as kHz.

Here are some traces of the trigger signal:

CH1: oscillator output Q COMPLEMENT
CH2: reset trigger signal

trigger_oscillator

Close-up on the trigger signal:

trigger_edge

7-Segment CD4026 Display

The counter is based on the classic CD4026 “bucket-brigade” configuration

Input Modulation

A signal may be directly fed into the CD4026 chain. That works fine as long as the signal is suitable.

With a 2V p-p sine wave directly connected with a 10nF decoupling capacitor, the counter works up to 3MHz or so.

To get a little more headroom, I was able to extend the frequency range to just over 5MHz with a NE5534P op amp configured as an adjustable comparator.